1. Field of the Invention
The present invention relates to flip-flop circuits. More specifically, the invention relates to amplifier-based flip-flop circuits for using in high-performance processors.
2. Description of the Related Art
Microprocessor architectures are continually evolving to improve and extend the capabilities of personal computers. Execution speed, power consumption, and circuit size are aspects of microprocessors and microprocessor performance that are constantly addressed by processor architects and designers in the ongoing quest for an improved product. Execution speed not only depends on the clock rate of a processor, but also upon the speed of interfaces such as cache memories and buses that supply instructions and data for execution by a processor core. The execution speed of microprocessors is heavily analyzed and compared using standard benchmark tests for judging the performance of competing entries into the microprocessor market.
Hold time is an important characteristic of electronic circuits that is specified to particular tolerances in a circuit design. Unlike setup time, variations of which are tolerated by slowing down the system clock, failure to meet the hold time specification result in a nonfunctional part. Currently a popular technique for setting hold time to defined tolerances is by insertion of delay cells between flip-flops. A difficulty with the usage of delay cells is that care must be exercised to avoid slowing down critical timing paths.
Referring to FIG. 1, labeled prior art, a schematic circuit diagram illustrates a conventional strobed amplifier flip-flop (SAFF) 100 including a strobed amplifier 102, followed by an RS-latch 104. The strobe amplifier flip-flop circuit 100 has a very good hold time due to the snapping nature of the amplifier input stage 102. Once the strobed amplifier 102 switches, a later change of input data D cannot overpower the strobed amplifier 102 and alter the state of the flip-flop 100. However, the RS-latch 104 includes two slow gate delays through cross-coupled NAND-gates 106 that adversely impact the CLK-to-Q performance of the strobe amplifier flip-flop circuit 100.
What is needed is a flip-flop circuit having a short latency and small hold time and is thus suitable for usage in high-performance VLSI circuitry.